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A new radio Communicate Architecture. Specifically, the software programmable radio is DSP Or CPU As the center, will be modular, standardized hardware module connected with the bus, which form General Hardware platform and software load to achieve a variety of wireless communication open architecture. With the development of communications, high-speed transmission technology lead to extensive research and attention. So far, the wireless transmission rate is limited by hardware conditions. To achieve high-speed transmission, we must combine the characteristics of a variety of chips, so hardware platform with a simple, common characteristics, it needs to develop a common platform. DSP in control and signal processing advantage, base band signal modulation, demodulation and FFT / IFFT and other operations can be achieved by the DSP, but in real-time processing by the DSP processing speed and capacity of existing constraints . For burst detection signal processing of this large amount of computation, especially in the high-speed transmission, usually using FPGA. FPGA-specific design of the pipeline structure allows concurrent in time before and after class, high efficiency and high speed. DSP signal processing in order to reduce the pressure on, while meeting the speed requirement, with a dedicated digital conversion chip digital down conversion. And software radio for thinking, consider the compatibility in the system design for single carrier modulation and demodulation using DSP, FPGA, up and down Inverter The program does not use dedicated modem chips. 1 OFDM principles and baseband signal model Orthogonal Frequency Division Multiplexing [1] OFDM (Orthogonal Frequency DivisionMultiplex) is a multi-carrier modulation, by reducing and eliminating intersymbol interference effects to overcome the frequency selective fading channel. Its basic principle is that the signal is divided into N sub signal, then modulating the signal with N sub N a mutually orthogonal subcarriers. As the sub-carrier spectrum overlap, which can get a higher spectral efficiency. In recent years, wireless communications, OFDM has been widely applied. When modulated signal reaches the receiver through the wireless channel, due to multipath effects of ISI caused by the role of sub-carrier orthogonality between the state is no longer good, and therefore the need to send the former Code element inserted between the guard interval. If the guard interval larger than the maximum delay spread, all the delay less than the guard interval of the multi-path signals will not be extended to the next symbol period, thereby effectively eliminating the intersymbol interference. When using single-carrier modulation, in order to reduce the impact of ISI and the multi-level equalizer, which will face higher convergence and complexity of the problem. Figure 1 is the OFDM baseband signal processing schematic. Among them, Figure 1 (a) is Transmitter Works, Figure 1 (b) is the receiver works. Figure 1 OFDM baseband signal processing diagram At the transmitter, first bit QAM or QPSK modulation stream, followed by string, and after transformation and IFFT transform, then the parallel data into serial data, plus guard interval (also known as " Cycle Prefix ") to form OFDM symbol. In the group frame, requiring the addition of synchronization and channel estimation sequence sequence to the receiver for burst detection, synchronization and channel estimation, the final output quadrature base band signal. When the receiver detects the signal arrives, the first synchronization and channel estimation. When the complete time synchronization, frequency offset estimation and correction of small times, after a FFT transform, for integer frequency offset estimation and correction, then the data is QAM or QPSK data that have been adjusted. Corresponding to the data demodulation, bit stream can be obtained. Discuss here only the software function modules, the specific algorithm is not here involved. 2 hardware OFDM modulation and demodulation, compared with conventional modem, large amount of computation required, especially when the system selected number of sub-carriers for a long time, only the IFFT at the transmitter and the receiver of the FFT transform transformation required time very long. Commonly used high-speed FPGA and DSP to solve the problem. Since the completion of the signal at the receiving end but also burst detection, synchronization and frequency offset correction digital signal processing, so the receiver of the real-time demanding. In this system, using FPGA to complete the burst signal detection and time, DSP complete the FFT / IFFT transform and QAM / QPSK modulation and demodulation. The system consists of four components: DSP, FPGA, quadrature digital upconverter (QuadratureDigital Upconverter), quadrature digital downconverter (Quadrature DigitalDownconverter). Hardware structure shown in Figure 2. The figure, D, said data bus, A bus, said address, C, said control bus, L chain junctions that data lines, the letters behind the numbers indicate the number of bits bus. 50MHz crystal for the two DSP and FPGA to provide the clock signal, 32.768MHz crystal oscillator of high stability for the AD9857 and AD6654 provide high-quality clock signal. Reset chip MAX6708 control DSP, FPGA, AD9857, AD6654 and ST16C550 reset. Chart 2 hardware structure DSP complete the QAM or QPSK modulation and demodulation and FFT / IFFT transform. System uses DSP [2] is the ADI's Tigersharc TS101. The DSP has the following characteristics: a maximum operating frequency of 300 MHz, 3.3ns instruction cycle; 6MB on-chip SRAM; 2 compute modules, each has an ALU, 1 multipliers, a shift register and a registers; two integer ALU, used to provide addressing and pointer operations; 14 DMA controller; 1149.1 IEEE JTAG port. For the OFDM baseband processor, the DSP is characterized by the greatest: for 256 points complex FFT transform, only 3.67 s. Quadrature Digital Upconverter with ADI's AD9857. AD9857 [34] The maximum operating frequency of 200MHz, the output IF frequency range is 0 ~ 80 MHz; internal integration and a half band filter, C IC (Cascaded Integrator Comb) filter, anti-SINC filter and high-speed 14-bits D / A converter, its core is a continuous phase of the direct digital synthesizer DDS (Direct DigitalSynthesizer). In the program, AD9857 work in the orthogonal modulation, the 32-bit frequency control word so that the maximum output frequency accuracy: SYSCLK (system clock) divided by 232. Quadrature digital down converter with ADI's AD6654. AD6654 [5] has an integrated 14-bit, 92.16Ms ps The analog / digital switch We are high quality suppliers, our products such as car key blanks , automotive key blanks Manufacturer for oversee buyer. To know more, please visits auto key blanks.
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