Digital network video monitor in the multi-relay logic design and implementation

Package Including a brief video monitor Board Principle, the adapter logic role in the system and the status and details of this logic with FPGA design and implementation process.

With the ever-changing technology, video surveillance market has been rapid development. Video Surveillance with its convenient, intuitive, content-rich and widely used in many occasions. In recent years, with the large-scale popularization of the Internet, and computer, networking, and image processing, transmission technology, the rapid development of video surveillance technology has made great progress. Video surveillance has been infiltrated Education , Government, entertainment, Hospital , Hotels Sports Venues , And other areas of the city public security, video surveillance Server Known as the following Mobile After another extremely promising market development Consumption Electronic Products.

Digital network video surveillance server to complete the main access from the camera's analog signal to digital compression capabilities delivered to the network, its block diagram shown in Figure 1.

Figures Figure 1 Block diagram of network video surveillance server

Shown in Figure 1, monitors the main circuit board by the A / D chip, FPGA multi-adapter chips, compression chips, CPU Etc.. Which this article to introduce the multi-FPGA implementation of logic in the adapter A / D chip and between the compression chip, due to the internal FPGA contains a PLL module, so the connection with the TW2804 chip FPGA 27MHz input clock can be generated from the FPGA.

Here use Altera's Cyclone series of EP1C6Q240C8, its internal 90k of storage capacity, 6kLEBS, 2 PLL, at the back of the design presentation, will be referred to throughout the design used in the 64k of storage capacity, 1 a PLL, about 4? 5k about LEBS, so use this low-cost FPGA, you can complete this design, but basically the majority of the full use of internal resources, combined with the chip's pin 240, to meet outside pin connections, so this logic Altera's EP1C6Q240C8 be the best choice of device design.

Shown in Figure 1, A / D chip to accept the four cameras from four analog video signals, where use of Techwell's TW2804 chip, the chip supports four video analog signal input and output digital IT U-RBT.656 format signal, the clock is 27MHz. D1, D2, D3, D4 signal timing diagram shown in Figure 2.

Figure 2 ITU-R BT.656 format signal timing diagram EAV and SAV

which were the first signs to end of line and line signals, among them is the gap between lines signals, SAV back VALID valid signal d1 to 1440bytes of the effective video signal format, the total These signals add up to a video signal line signal, a video signal including the 576 line so the line signal, which is effective this format an output video signal to 1440 * 576bytes signal, as each line signal from the two bytes to Table Show a pixel, so that d1 format a 720 * 576 pixels resolution.

FPGA logic to achieve the switching function is to display terminal on the same show four of the video signal. Is shown in Figure 3 to display the video signal.

As a display terminal to show four signals at the same time, so every way the original 720 * 576 resolution signal to convert the original 1 / 4 resolution, the cif format, cif format is 352 * 288 resolution, so that four cif format signals to form one shown in Figure 3 frames output to the terminal is displayed.

As is required in the terminal display four simultaneous video signal output, which is not allowed in the way in which the signal has been Monitor Show up, but also the way the signal has not shown, which is part of the screen is black screen appears the situation, so in this case, the need to four different video signals in the first use of FPGA cached in the SDRAM, when Each stream is kept in the SDRAM of at least one full time can be read simultaneously, and the composition of the internal cache by FPGA as shown in Figure 3, the frame format, and then output to the compression after the chip compression Processor Control output to a network, where the election is VWEB compression chip companies VW2010.

Figure 3 shows the terminal video signal format

This point, FPGA to realize the function has been very clear, first of all input signal formats were four d1 into four cif format signal, then these four signals in the SDRAM buffer, respectively, when SDRAM signals for each of at least one is full, the synchronous read, read out to the FPGA, SDRAM, after a realignment of the format, the final form as shown in Figure 3, the signal format output. SDRAM in which data in the cache control is the most important and most complex part. The following details the FPGA logic design and implementation.

Known by the above description, three main aspects of this FPGA interface, and TW2804's input interface, and SDRAM cache interface, and VW2010 the output interface. Therefore, the internal logic of FPGA design as roughly shown in Figure 4.

Figure 4 FPGA block diagram of the internal logic

Input format conversion module of the completion of four signals from d1 to cif format conversion, from the original 720 * 576 pixel resolution 352 * 288 pixels is converted to a resolution. The conversion process is to an even number of rows in all the data removed, each line separated by one pixel in order to remove one of the last to retain the original data is 1 / 4 of the data. This process is relatively simple, two ranks of the counter through the design can be achieved. The simulation shown in Figure 5.

Figure 5 d1 to cif format diagram of a simple simulation

Shown in Figure 5 in the odd rows of data to an empty one valid reading in a row, the next row are set to invalid.

Followed by the internal input buffer module, this module is used to control and SDRAM control and data cache connected to the control module. Its internal logic diagram shown in Figure 6.

Figure 6 FPGA internal buffer SDRAM controller connected with the internal logic diagram

Following can be given on the design of future

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