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With the rapid development of electronic technology, more and more people join the ranks of e-development. Electronic technology in the learning process and R & D projects, to avoid not to use some instruments, such as multimeter, oscilloscope, etc., but for some non-professional enthusiasts, with a digital oscilloscope is a more "extravagant". The Design of digital oscilloscope, because of its low cost, make a simple and high accuracy advantage of people just to meet this demand. Create a simple oscilloscope, but to produce high analog input bandwidth of the oscilloscope is not easy. The choice of the main device is designed for high analog input bandwidth goals. This C8051F020 MCU used as the CPU, it has 51 simple cores and I / O is rich in resources. A / D use 8-bit high speed A / D converter TDA8703, the maximum sampling rate of 40 Msps. In addition, the use of dual-port FIFO-IDT7202LA-12, it is the FIFO dual port memory, the fastest time into 12 ns. The system includes front-end analog signal conditioning circuit module, the signal acquisition circuit module, the signal transmission module, the chip logic control circuit module, display module. A front-end analog signal conditioning module circuit The LM6361 amplifier module using high-speed and high-speed comparator AD744, shown in Figure 1. The design selected product probe. In order to prevent over-voltage input, high-speed comparator AD744 front plus two protection diodes clamp the input signal to ± 12 V, the protective effect on the entire system. Then after ICI reverse amplification, and then by IC2 signal to phase back into the initial phase. Since the design uses the AD voltage input range of 1.55 ~ 3.26 V, so application IC3 plus a DC component to the input signal "carried to" A / D input range. 2 signal acquisition circuit module The module's A / D converter is the TDA8703. It is the Philips company's high-speed analog / digital converter, the sampling rate is 40 Msps, 8-bit resolution, signal to noise ratio is high, with TTL-level compatible with the internal reference voltage. TDA8703 input voltage and output binary code as listed in Table 1, sample sequence shown in Figure 2. Clock rising edge arrives began sampling the clock rising edge of the next cycle of rise, the end of conversion. Since up to 40 Msps sampling rate, the ordinary single chip difficult to "keep pace", this time using dual-port RAM?? IDT7202, used in conjunction with them to achieve the purpose of synchronization with the single chip. IDT7202 is a launch of an advanced, AMD / before the dual-port memory. The model used in this design is IDT7202-12, which is deposited in the data processing time is 12 ns, to deposit frequencies up to 83 MHz, can match with 40 Msps in the AD, so two chips use the same clock sampling and storage ( shown in Figure 3). IDT7202 a depth of 1 024-byte of storage, low power, CMOS process, there are three kinds of status flags (empty, half full, full), industrial grade temperature (1 40 ~ 80 ). TDA8703 sampling clock signal with IDT7202 write access the same clock, this will make the two sync. When the sample 1 024 points, closing the sampling clock signal, IDT7202 the FF side low effective, CPU to the data IDT7202 IDT7202 out, and check the empty flag side; when the low effective, meaning the data in all IDT7202 is removed, then re-open the sampling clock signal, repeating the process. As shown in this design uses a PC, uploaded by the serial port baud rate limitations, it is difficult to measure high frequency signals, while the design is precisely a certain extent, solved the problem. As the 1 024 samples is continuous, can be gradually formed a complete waveform upload. However, the 1 024 sampling points in the process of uploading to a PC, the ADC sampling is prohibited, so the PC, see the waveforms are not continuous "joint." However, for simple digital storage oscilloscope is "tolerance". In the design process, because too many traces, so even if the pilot phase have to do PCB board; However, with each chip control logic between the uncertainty, it is prone to error. Time to build this system using CPLD logic circuit, once the error, you can modify at any time until the right. If after the success of the entire system debugging, use and, or, non-replacement of the logic circuit CPLD, this would reduce costs. 3 signal transmission module The design of the CPU is responsible for signal transmission is C8051F020. C8051F MCU is a fully integrated mixed-signal system-on-chip, compatible with the 8051 controller core, and MCS-51 instruction set compatible; addition to the standard 8051 with the number of peripheral components, the chip also integrates data acquisition and control systems commonly used in analog parts and digital peripherals and other features. C8051F MCU pipelined, machine cycle from the standard 12 system clock cycles reduced to a system clock, with greater capacity, peak performance of up to 25 MIPS. C8051F MCU is able to work in a truly independent system on chip (SoC). Each MCU can effectively manage analog and digital peripherals, you can close individual or all of the peripherals to conserve power. Flash memory also has the ability to reprogram the chip can be used for non-volatile data storage, and allow on-site firmware update 8051. On-chip JTAG debug support function allows the use of applications installed on the final product on the MCU in non-invasive (do not take up system resources), full speed, the system debugging. The debug system to support observation, modify memory and registers, to support breakpoints, single step, run, stop command. Using the JTAG debug, all analog and digital peripherals can run all functions. C8051F compatible with standard 8051 I / O port. Some ports in some of the devices did not lead to foot, so the port can be used as general purpose registers. I / O port similar to the work of 8051, but some improvement. Each port I / O pins can be configured as push-pull or open-drain output. Fixed in 8051 in the standard "weak pull-up" can be disabled, low-power applications that further power-saving capabilities. The most striking improvement is the introduction of a digital crosspoint switch. This is a big digital switch network, allowing the internal digital system resources allocated to the port I / O pins. And a standard multiplex digital I / O micro-controllers, this structure can support all the features combined. Can set the crossover switch control register, to film the counter / timers, serial bus hardware interrupt, ADC conversion start input and the internal micro-controller and other digital signal is configured to appear on the port I / O pins. This allows the user to choose according to their specific application common port I / O and a combination of digital resources required. I am an expert from trk.cc, while we provides the quality product, such as Mini GPS Pet Tracker Manufacturer , Package Tracker Manufacturer, GPS Pet Locator,and more.
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