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Deep sub-micron IC design technology used in chip integration makes the larger, smaller and smaller, more and more pins; In recent years the development of IC technology, making it higher and higher speeds. Thus, making the signal integrity problems caused by electronic designers attention. In video processing systems, multi-dimensional parallel input and output signals of the frequency in megahertz hertz generally, but also very strict timing requirements. In this paper, DSP image processing system for the background, the theory accurately signal integrity analysis, signal integrity of the typical problems involved [1]?? Uncertainty, the transmission line effect, reflection, crosstalk, ground bounce and other in-depth study, Starting from the actual system and the use of IS simulation software to find effective ways to solve the system's signal integrity issues. 1 Introduction Order to improve the efficiency, real-time processing image information, the image processing system is based on DSP + FPGA Structural design. System consists of SAA7111A video decoder, TI's TMS320C6701DSP, Altera Corporation EPlK50QC208 FPGA, PCI9054 PCI interface controller and SBRAM, SDR AM, FIFO, FLASH and other form. FPGA is the timing of the system control center and a bridge for data exchange, but also the bottom of the image data for fast processing. DSP is a high-level algorithm for real-time processing throughout the system, the core of the device. System block diagram shown in Figure 1. In the whole system, PCB circuit board area of only 15cm × l5cm, the system clock frequency up to 167MHz, the clock along the time of 0.6ns. As the system has a fast slope of the transient and high operating frequency and a lot of circuit density, making the problem how to deal with high-speed signal design as a key success factor constraints. 2 system signal integrity problems and solutions 2.1 the mechanism of signal integrity problems Signal integrity is the signal transmitted through the physical circuit, the signal receiver to see the waveform and signal transmitter to send the waveform within the allowed range of error is consistent, and space the transmission of signals between neighboring interaction is also within the limits. Therefore, the signal integrity analysis of the main goal is to ensure reliable high-speed digital signal transmission. There is always the actual signal voltage fluctuations, shown in Figure 2. In A, B two points as overshoot and ringing of [2] existence of the signal amplitude into the shaded area of uncertainty may lead to wrong logic level occurs. Bus signal transmission more complicated, any signal lead or lag phase on the data bus can make mistakes, as shown in Figure 3. The figure, CLK is the clock signal, D0, D1, D2, D3 is the data bus signals, the system allows the signal maximum up time [1] as t. Under normal circumstances, D0, D1, D2, D3 signal setup time t1 t, t time in the data bus after the data has stabilized, the system can be sampled from the bus to the correct data, shown in Figure 3 (a) shown. On the contrary, when the signal D1, D2, D3 received red and ringing signal integrity problems such as interference, the bus signal on the occurrence of the phase shift and distortion, so that D0, D1, D2, D3 signal setup time t2 t, t time the system will get the wrong data on the bus, the control error signal, disrupting the normal work in order to signal integrity problems more complex, shown in Figure 3 (b) below. 2.2 Signal reflection Signal reflection refers to the transmission line ends there echo. When the transmission line impedance discontinuities, they will lead to the occurrence of signal reflections. Here, as shown by Figure 4, the ideal transmission line model to analyze the signal reflection of important parameters. In the figure, the ideal transmission line L is the internal resistance as the driving source signal Ro Vs the number of drivers, transmission line characteristic impedance Zo, the load impedance RL. Critical impedance in the case, Ro = Zo = RL, the impedance of the transmission line is continuous, without any reflection. As in the real system is difficult to satisfy the critical damping, the most reliable way for a slight over-damping, since this is not the source of energy reflected back end. Load impedance and transmission line impedance mismatch at the load side (B point) part of the signal reflected back to the source side (A point), the amplitude of the reflected voltage signal Load reflection coefficient of several decisions, the following formula can be derived: PL = (RL-Z0) / (RL + Z0) (1) The formula, PL as the load voltage reflection coefficient, it is actually reflecting the ratio of voltage and incident voltage. From (1) know that? 1 PL +1, when RL = Zo when, PL = 0, reflection does not occur. Can be seen, as long as the characteristics of the transmission line impedance matching terminals can eliminate reflection. Theoretically that the magnitude of reflection wave can be as large incident voltage amplitude, polarity can be positive or negative. When RLZo time, PL 0, is due to damping, the reflected wave polarity is positive. When reflected back from the load side when the voltage reaches the source, in turn reflected back to load again to form a second reflected wave, then the amplitude of reflected voltage from the source reflection coefficient PS decision obtained by the following formula: Ps = (R0-Zo) / (R0 + Z0) (2) In the high-speed digital systems, the transmission line length line termination technique should be used the following formula: L tr / (2tpdl) (3) The formula, L for the transmission line length, tr for the source-side signal rise time, tpdL for the transmission line per unit length of the zone set propagation delay. That is, when tr is less than 2TD (TD for the propagation delay), the source end complete level transfer will occur in the receiver from the transmission line reflection back to the source side of the reflected wave reaches the source-side before the termination matching technology which requires otherwise, in the transmission line caused by ringing. Combination of Figure 1 Design of the system, using MentorGraphics company's signal integrity analysis tools InterconnectSynthesis (IS), signal drivers and receivers are used TTL_S IBIS device model technology circuit simulation, select the correct Wiring Strategies and termination methods. DSP and SBSRAM interface clock up to 167MHz, the clock transmission and minimal delay, it is easy to reflection phenomena occur in the signal line. According to the formula (2), to eliminate the source end of the reflected wave must be conducted in the source side impedance matching, so that PS reflection coefficient of 0. Simulation with interconnectSynthsis Test Availability of transmission line of this clock The e-commerce company in China offers quality products such as portable industrial scales Manufacturer , electronic truck scale Manufacturer, and more. For more , please visit weight counting scales today!
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