Dennis Buss, a visiting scientist at theMassachusetts Institute of Technology (MIT) and consultant at TexasInstruments (TI), presented "Research in self-poweredelectronic systems (#10.4)" at IEEE's International ElectronDevices Meeting (IEDM) recently. He shares key results here. Ultra-low-power systems operate in the range of a 100microWatt to afew milliVolts; one way to do this is to go to ultra-low voltage --around 0.5volt is typical. Medical monitoring/health monitoringelectronics can become self-powered systems that would preclude theuse of wires or batteries that need to be removed and replaced.Also, wireless sensor networks (WSN) can be used for suchapplications as smart buildings that do not require a permanentsource of energy. One key result in Buss' IEDM paper was an MSP430 chip designed tooperate below threshold: a VDD of around 0.3V.
Compared to thecommercial product, the chip achieved an energy/operation reductionof a factor of 10x. The chip had on-chip SRAM, on-chip DC/DCconverter and a fair amount of logic. Another result: an ultra-low-power medical DSP fabricated in a130nm low-leakage process. This chip operated down to 05.V andsurprisingly used accelerators.
(e.g. FIR and FFT filters, andother algorithms commonly used in medical monitoring). Two technical challenges exist. Random dopant fluctuation-inducedlocal variations occur.
When you operate at very low voltage, thevariations in threshold have a huge -- exponential -- effect onlogic timing. "There is no way to make a corner model thatcomprehends accurately the effect of local variations," saysBuss. What his team shows is that, at low voltage, the 3-sigmastochastic delay resulting from local variations can exceed thecorner delay, so it must be accurately understood. When we designchips today, Buss says, the predominant process variation is global-- affecting all logic gates on the chip in the same way.
Forexample, if the gate length is a little on the long side, it'sprobably long for all the devices on a chip. "If we'reinterested in the slow corner, we can generate a set of models thatwill comprehend the 3-sigma worst-case global delay for thesevariations. We don't simulate the nominal models, we simulate tothe worst-case slow and worst-case fast models. In the case ofrandom dopant fluctuations, the transistors are not all affected inthe same way; in fact, they are all different. When you combine thestochastic effects of different transistors, you have to add themin quadrature (like the square root of the sum of the squares) andthis requires a new methodology for timing." Another technical challenge is systems aspect.
In some sense, we'vedemonstrated all the pieces -- logic, AFE, A/D converter,ultra-low-power radios, energy management, switch capacitor DC/DCconverters, and energy harvesting devices -- but we still don'thave a system that responds to real needs, Buss says. Two systemaspects are particularly demanding: the needs of computation varydramatically (throughput) and unreliable energy sources thatrequire battery back-up. Listen to Buss discuss the paper: See more paper summaries from IEEE's IEDM: imec presents MEMS energy harvester at IEDM SuVolta's DDC transistor technology @ IEDM SEMATECH s SILC ~10% and HKMG lifetime; ALD BeO a viable gatestack IPL solution Cornell, SRC develop RF MEMS technologies IBM displays via-middle TSV process for die stacking Intel clarifies 32nm NMOS stress mechanism at IEDM 2011.
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