Synopsys announced the availability of the 2013.03 release of its IC Compiler software. This latest release features innovation, advanced optimization to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO), support for the emerging FinFET-based silicon processes as well as enables the latest process nodes. Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group said, "We continue to deliver technology innovations that target pressing customer needs. Companies like Mellanox Technologies who are doing advanced design with strong time–to-market demands will benefit from new technologies for faster ECO closure and high-speed clock design. Combined with our strong focus on emerging node technology, these advanced capabilities reinforce IC Compiler’s position as the preferred implementation choice across the IC design community." The IC Compiler release also include new features to deliver faster design closure. One important new capability is the application of final-stage ECOs to close the design. IC Compiler, working hand-in-hand with Synopsys' PrimeTime signoff solution, provides a highly efficient ECO solution rooted in dual principles. Combined with a fully automatic, incremental In-Design physical verification capability, IC Compiler provides a significant reduction in turnaround time for ECO closure. The release enables high-speed clock design by performing clock estimation during placement to drive physical- and timing-aware clock gating concurrently with clock and data optimization to achieve the target frequency faster. It provides tapeout-proven FinFET support for emerging process nodes.
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