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Intel finfets vary, may need soi for shrink, says gss by ferujkll sdff
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Intel finfets vary, may need soi for shrink, says gss |
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LONDON Intel's 22-nm FinFETs show physical variability accordingto cross-sectional photographs from engineering consultancyChipworks Inc. (Ottawa, Ontario) and EDA company Gold StandardSimulations Ltd. (GSS) has attempted to model electricalcharacteristics of various examples. One conclusion drawn by Professor Asen Asenov, CEO of GSS (Glasgow,Scotland) is that Intel may need to turn to silicon-on-insulatorwafers to scale its FinFETs below 22-nm. This may also haveimplications for foundries which are yet to introduce FinFETtechnology into their chip manufacturing processes.
GSS has already done some TCAD simulation of FinFET and postedfindings in a blog that discussed the fact that at 22-nm Intel'sFinFETs are trapezoidal rather than rectangular in cross-section(see Intel's FinFETs are less fin and more triangle ). The latest GSS blog seeks to compare the on-current of differently shaped FinFETs. Itpoints out that in logic applications multiple fins are connectedin parallel, resulting in an averaging of their characteristics,but in SRAM circuits the variability in the single fin is a keycharacteristic and performance limiter. TEM images of three Intel FinFETs with the GARAND simulation domainoverlaid.
Source: GSS The characteristic dimensions of three FinFETs were fed into theGSS Garand simulator and revealed that at 22-nm, nature appears tohave worked to Intel's advantage. "Despite significant differencesin the shape of the three fins, the difference in the on-current iswithin a 4 percent range," the blog states. "Compared with process variation across the chip or across thewafer 4 percent is small. But it is additional variation,"Professor Asenov told EE Times . He added that the simulation revealed that FinFET processtechnology is complex and difficult to implement, partly because ofthe lack of a planarization process that can level-up shallowtrench isolation oxides between transistors.
One result of this isthat bulk FinFET heights can vary. Professor Asenov admitted that a number of assumptions have to bemade to allow the simulations to run. It is assumed that the finitself is virtually undoped but there is a punch-through stopperdopant region beneath the fin. "We don't know about dopant profilesand strain, but we have tried to make favorable assumptions," saidProfessor Asenov. Click on image to enlarge.
Dependence of on-current, I ON , on gate length. Source: GSS GSS has included results for simulations of rectangularcross-section FinFETs with 10-nm and 8-nm widths hinting at wherethe company thinks Intel must go next. "If you can make them[FinFETs] rectangular you will gain significantly in terms ofperformance, about a 20 percent gain." Professor Asenov said that moving from bulk FinFETs to FinFETsconstructed in SOI wafers could solve a number of problems. "Theburied oxide layer means you don't have the problem of fillingtrenches. The height of the fin is determined by the depth of thesilicon above the oxide." Professor Asenov added: "I think Intel just survived at 22-nm.
Ithink bulk FinFET will be difficult to scale to 16-nm or 14-nm. Ithink that SOI will help the task of scaling FinFETs to 16-nm and11-nm. Of course the wafers are more expensive, but you save moneywith less processing." Researchers from GSS and the University of Glasgow published apaper at the International Electron Devices Meeting of 2011 dealtwith FinFETs implemented in SOI wafers and how they could meet lowstatistical variability requirements of 11-nm CMOS. Related links and articles: GSS blog News articles: Intel's FinFETs are less fin and more triangle Startup offers 'variability' modeling service Glasgow University, Intel team up as part of EC memories taskforce. I am a professional writer from Other Luggage, Bags & Cases, which contains a great deal of information about beach cruisers bikes , attwood bilge pumps, welcome to visit!
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