April 26, 2012 -- After pioneering low-cost wafer- and panel-based glass and silicon interposers in Phase 1 of its SiGI consortium, Georgia Tech Packaging Research Center (GT-PRC) is beginning Phase 2 in June. The industry consortium involves about ~30 semiconductor, package, and related supply-chain companies from the US, Europe, and Asia. They developed glass and silicon interposers with 10x higher I/Os than conventional organic packages, at 2-10x lower cost per mm2 than back end of line (BEOL) silicon interposers. SiGI Phase 1 has demonstrated technologies to: handle ultra-thin glass and silicon wafers and panels, form small through-package vias (TPV) at fine pitches with high throughput and high reliability, and make 5µm double-sided re-distributed layers (RDL) on both sides of ultra-thin glass and silicon panels with 10x lower signal loss than oxide-lined TSV interposers. Chip-to-interposer cu-bump interconnection has been demonstrated at 50µm I/O pitch. The 2-year Phase 2 of this program, launching in June 2012, will build upon and expand on Phase 1, focusing on: thinner glass (30-100µm) and its handling multi-level RDL with 3µm lines and spaces and 5µm vias Cu-to-Cu chip-to-interposer interconnections at 15-50µm pitch and their reliability Low standoff and fine pitch gap fill Reliable SMT interconnection to PWB with large package sizes Enhanced thermal dissipation of glass interposers to that of Si interposers High performance and thinfilm passives as IPDs or thin planar layers Electrical, thermal, mechanical and thermo-mechanical modeling and characterization Selective module demonstrators in Power, Analog, Digital, RF, mm-wave, MEMS and LED Packaging applications Georgia Tech PRC plans to partner with R&D and manufacturing supply chain companies to bring about advances in materials, processes, tools modeling and designs.|
Interested companies can contact Dr. Venky Sundaram at firstname.lastname@example.org, 404 894-9394 or Prof. Rao Tummala at email@example.com, 404 894-9097. GT-PRC will be holding an Open House for companies interested in joining the SiGI Phase 2 Consortium, May 25, 2012, 8:00am-noon, Georgia Institute of Technology. Learn more about Georgia Tech’s 3D Systems Packaging Research Center at www.prc.gatech.edu.
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